The present invention relates to ultrasound imaging systems of a sector scan type using a linear array of piezoelectric transducers, and in particular to a method and apparatus for scanning the main ultrasound beam of the transmitted acoustic energy based on stored digital information representing the delay time between adjacent transducers.
It is a well known fact that when the piezoelectric elements are activated simultaneously the acoustic energy transmitted therefrom forms a main ultrasound beam whose axis is perpendicular to the linear array and when they are activated successively at different timing the axis of the main beam is deflected at an angle to the perpendicular depending on the amount of the time differential between adjacent transducers.
In a prior art method, the delay times are represented by digital data and stored in a memory from which the data for each of deflection angle of the main beam is retrieved. Therefore, the number of bits to be stored in the memory would amount to L.times.M.times.N, where L is the number of discretely varying deflection angles, M is the numbe of bits required to represent the delay time to be introduced to each transducer element, and N, the total number of the transducer elements. Assume that L=100, M=8 and N=32, the total number of bits is 25600 bits, or 3200 bytes. This number represents a substantial amount of storage capacity and a complicated control circuitry would be required if the linear array is activated at a high speed.
To solve this problem Japanese patent application No. 50-135082 laid open to public inspection under publication No. 52-59974 on May 17, 1977, discloses an apparatus in which L.times.N bits of time delay data are stored in a read-only memory and each set of N bits is transferred to an N-bit shift register in parallel form. The shift register is driven by clock pulses to shift the received data in succession. The parallel outputs of the shift register are thus varied discretely by the amount of "1" bit at the most and applied through parallel gates to respective up-down counters which are associated with respective piezoelectric transducers. The length of period during which each gate is held open depends on the total number of "1" bits successively stored in each bit position of the shift register, so that by supplying through the associated gate each up-down counter is preset to a different count value which represents the time the associated transducer is activated with respect to a reference time. The up-down counters are then driven by high frequency input pulses and deliver carry output pulses successively to the transducers when the preset count values are reached.
However, in the disclosed prior art system the binary differential value or time difference between adjacent transducers is limited to a single bit and since it is desirable to have a binary differential value of more than 1 bit for purposes of achieving a greater angle of deflection, the disclosed system falls short of the ideal.
Furthermore, the memory capacity required for the prior art system is L.times.N bits which would amount to 3200 bits or 400 bytes on the assumption that L=100 and N=32 which are the typical values of a practical embodiment. This is a substantial amount of memory and reduction of this capacity is desirable for purposes of economy.